Digital Hardware Engineer with hands-on experience in RTL design, IP core development, and FPGA prototyping.
Enjoys building systems from transistor-level layouts to digital integration. Skilled in Verilog, C, and EDA tools.
Technical Skills
/dev/nvme0n1p2
Languages
Verilog
C
Assembly
Python
Tools
LTSpice
Microwind
GTKWave
Quartus
Vivado
Scilab
Design Areas
RTL Design
Analog Simulation
FPGA Prototyping
Digital Layout
Boards
Altera DE2
Zynq-7000
Work Experiences
@DPTek: Feb.2025 - Present
Development in Bluetooth-based embedded system project, focusing on Nordic nRF52832 development kit:
Developed Bluetooth Low Energy (BLE) communication protocols, implementing both Peripheral and Central roles
Familiar with Zephyr RTOS: configured device tree, built system modules, and integrated BLE stack using Zephyr build system (west, Kconfig, prj.conf)
Serial Protocols: I2C, UART, 1-Wire & FSM Control (Verilog)
Integrated with temperature sensors and LCD, deployed on Altera DE2 FPGA.
4-bit ALU in Verilog (Vivado, GTKWave)
Designed and verified a modular ALU supporting ADD, SUB, AND, OR operations. Simulated waveforms and deployed on Basys3 Xilinx board.
CMOS NAND/NOR, Half-Adder Layout (Microwind)
Created layout and analyzed sizing, area, and logical correctness.
6T SRAM Cell Design (LTSpice)
Simulated stability and performance of 6T SRAM under read/write operations.
8086-microprocessor Assembly Programming
Wrote 8-bit multiplication, 16-bit addition/subtraction routines using registers and memory.
Signal Modulation Techniques (SciLab)
Explored and simulated Analog, Frequency, and Digital Modulation schemes using SciLab. Demonstrated signal transformation and spectrum analysis.
Op-Amp Band-Pass Filter (LTSpice)
Designed and simulated active filter using 741 Op-Amp. Verified frequency response via AC analysis.
RFID-RC522 & PWM Servo Module Integration
Designed a toll station management system using the RFID-RC522 module on ESP32, programmed via Arduino IDE. Data was transmitted to the cloud using the Blynk IoT platform.